Q & A on Hardware Technologies

Q: CNAI, p.32D. Does the fact that Ethernet uses CSMA/CD preclude an Ethernet system from using frequency division multiplexing? That is, does the existence of one carrier wave on the ether keep every other host off?

A: Yes. When one host is transmitting on a segment (or a hub) other hosts refrain from transmitting. You can imagine that they all use the same "frequency". Thus, there is no FDM.

Q: Is X25net a connection oriented technology?

A: Yes. Like ATM, X.25 is connection-oriented.

Q: When you state that ' "tunneling" treats packets like data' do you mean this technique treats packets like a continuous stream of data where individual packets are sent contiguously, one after another?

A: Technically, the difference between *tunneling* and *encapsulation* is that encapsulation sends datagrams over hardware frames, while tunneling sends datagrams over some "higher level" protocol system. In terms of X.25 the term *tunneling* is appropriate because X.25 adds several layers of protocols on top of the underlying hardware.

Whether the interface is stream-oriented or message-oriented is completely independent of the underlying transmission scheme (e.g., TCP offers a stream-oriented interface, but sends data in individual segments, with one segment per datagram). Thus, one can tunnel over a stream-oriented interface or a message-oriented interface.

Q: LAN's vs. WAN's. Can the nodes of a LAN be a subset of the nodes of a WAN (or are they disjoint sets)? Are WAN's ever aggregates of LAN's?

A: The quick answer is that because LANs and WANs use completely different technologies, one cannot build a WAN by aggregating LANs. However.... some WAN technologies provide an interface that *appears* to be a LAN. For example, if one leases a satellite channel between San Francisco and new York, the equipment might appear as an Ethernet bridge to the computers using it. That is, a computer in San Francisco plugs into a 10BASE-T port, and appears to send and receive Ethernet frames. The bridge takes each transmitted frame, encodes it for transmission, sends the result across the satellite channel to New York, which then decodes the frame and delivers it to a 10BASE-T port. The advantage of using a 10BASE-T interface is that the attached computers can use standard hardware and software. That doesn't mean there's an Ethernet underneath (i.e., it's only the interface that appears to be an Ethernet). By the way, the same is true of ISDN and DSL technologies -- they accept and deliver Ethernet frames.

Q: Is it correct that a computer (host or router) has a physical address, but that its _connection_ to the Internet has an IP address? Or--is the physical address actually associated with the connection also?

A: Every network interface card has a physical address. If a computer connects to more than one network, it has more than one physical address. Thus, a router *always* has multiple physical addresses.

Q: Is the mapping from IP addresses to physical addresses one-to-one? In particular, if a host is multi-homed with two IP addresses, must it also have two physical addresses?

A: In almost all real internets the mapping is one-to-one. People sometimes play games where they assign *more* than one IP address to a given hardware interface (e.g. to simulate two subnets on the same physical wire). These many-one configurations fall outside the original intended use of IP. :-)

Q: In volume I you assert that routers must choose between routes employing physical networks that have properties of delay, throughput, and reliability. How do routers actually store this information? Is there some kind of static evaluation function the output of which characterizes the 'goodness' of a prospective route?

A: Although there has been much research on routing, the real Internet usually chooses the route that minimizes the hop count. Thus, the *type of service* routing field in the IP header is seldom used and the type of service routing you describe is seldom implemented. If it were, routers would need to keep detailed information about the throughput and delay along all paths. Delay changes so quickly that keeping accurate information is impossible.

Q: You state that each hardware technology imposes its own upper bound (MTU's) on frame size (e.g., Ethernet 1500, FDDI around 4K). Are all frames emanating from a given host 'A' of exactly the same size all the time? Do all hosts attached to Ethernet nets send frames of size 1500?

A: No, in most technologies, a frame is only as large as needed. For example, if you need to send 200 octets across an Ethernet, the outgoing frame will have a header followed by exactly 200 octets of data. For example, if a 600-octet datagram is sent over an Ethernet, the resulting frame has 600 octets of data following the Ethernet header.

As a practical matter, TCP/IP tries to optimize efficiency. Thus, if you use TCP/IP to transfer a file across an Ethernet, IP will create datagrams that are each 1500 octets long.

Another technical point: some technologies require a minimum frame size (so the hardware can distinguish real frames from a small burst of electrical noise or so the MAC protocols function properly). For example, Ethernet requires a frame to contain at least 64 octets of data. If the data being sent is less than the minimum size, it must be padded (e.g., with zeroes).

By the way, if a technology sends packets of a fixed size, they are called *cells*, not *frames*. For example, because each packet sent by ATM is the same size (53-octets), they are called *cells*, and ATM is known as a *cell-switching technology*.

Q: Please verify: when a host sends datagrams, they can be of *varying* size, but the frames emanating from the host will always be the same size.

A: Not correct -- both datagrams and frames can be of *varying* size.

Q: Are there actually two routing algorithms employed for forwarding data: one for frames on the physical net and one for datagrams on the virtual net?

A: In most LAN technologies, there is no "routing" -- one sends the packet across the LAN, all computers receive the frame, and all interface cards except the intended destination discard the frame. In most WAN technologies (at least the WANs that connect multiple hosts), the WAN needs to route frames among the switches that make up the WAN. Thus, when you send a packet across an X.25 network, switches inside the network route the packet from the port where it entered the network to the port where it exits.

So, the general answer is that routing occurs only at the IP level, not at the physical net (a handful of WAN technologies being the exception).

Q: Bridges vs. Routers: Can a bridge attach two different types of LAN's say, an Ethernet and a CDDI? How about an Ethernet and an FDDI?

A: In general, no. Bridges do not change the *shape* of the frame or the addresses. Thus, the technologies must have compatible frame formats and compatible addressing schemes. Thus, one could bridge CDDI and FDDI, but could not bridge Ethernet and FDDI.

CPU engineer interview questions

1. For a single computer processor computer system, what is the purpose of a processor cache and describe its operation?
2. Explain the operation considering a two processor computer system with a cache for each processor.
3. What are the main issues associated with multiprocessor caches and how might you solve it?
4. Explain the difference between write through and write back cache.
5. Are you familiar with the term MESI?
6. Are you familiar with the term snooping?
7. Describe a finite state machine that will detect three consecutive coin tosses (of one coin) that results in heads.
8. In what cases do you need to double clock a signal before presenting it to a synchronous state machine?
9. You have a driver that drives a long signal and connects to an input device. At the input device there is either overshoot, undershoot or signal threshold violations, what can be done to correct this problem?

Hardware architecture interview questions

1. Are you familiar with the term MESI?
2. Are you familiar with the term snooping?
3. Describe a finite state machine that will detect three consecutive coin tosses (of one coin) that results in heads.
4. In what cases do you need to double clock a signal before presenting it to a synchronous state machine?
5. You have a driver that drives a long signal & connects to an input device. At the input device there is either overshoot, undershoot or signal threshold violations, what can be done to correct this problem?
6. For a single computer processor computer system, what is the purpose of a processor cache and describe its operation?
7. Explain the operation considering a two processor computer system with a cache for each processor.
8. What are the main issues associated with multiprocessor caches and how might you solve it?
9. Explain the difference between write through and write back cache.
10. What are the total number of lines written in C/C++? What is the most complicated/valuable program written in C/C++?
11. What compiler was used?
12. Have you studied busses? What types?
13. Have you studied pipelining? List the 5 stages of a 5 stage pipeline. Assuming 1 clock per stage, what is the latency of an instruction in a 5 stage machine? What is the throughput of this machine ?
14. How many bit combinations are there in a byte?
15. What is the difference between = and == in C?
16. Are you familiar with VHDL and/or Verilog?

Hardware Interview Questions

x86 interview questions

These interview questions test the knowledge of x86 Intel architecture and 8086 microprocessor specifically.

1. What is a Microprocessor? - Microprocessor is a program-controlled device, which fetches the instructions from memory, decodes and executes the instructions. Most Micro Processor are single- chip devices.
2. Give examples for 8 / 16 / 32 bit Microprocessor? - 8-bit Processor - 8085 / Z80 / 6800; 16-bit Processor - 8086 / 68000 / Z8000; 32-bit Processor - 80386 / 80486.
3. Why 8085 processor is called an 8 bit processor? - Because 8085 processor has 8 bit ALU (Arithmetic Logic Review). Similarly 8086 processor has 16 bit ALU.
4. What is 1st / 2nd / 3rd / 4th generation processor? - The processor made of PMOS / NMOS / HMOS / HCMOS technology is called 1st / 2nd / 3rd / 4th generation processor, and it is made up of 4 / 8 / 16 / 32 bits.
5. Define HCMOS? - High-density n- type Complimentary Metal Oxide Silicon field effect transistor.
6. What does microprocessor speed depend on? - The processing speed depends on DATA BUS WIDTH.
7. Is the address bus unidirectional? - The address bus is unidirectional because the address information is always given by the Micro Processor to address a memory location of an input / output devices.
8. Is the data bus is Bi-directional? - The data bus is Bi-directional because the same bus is used for transfer of data between Micro Processor and memory or input / output devices in both the direction.
9. What is the disadvantage of microprocessor? - It has limitations on the size of data. Most Microprocessor does not support floating-point operations.
10. What is the difference between microprocessor and microcontroller? - In Microprocessor more op-codes, few bit handling instructions. But in Microcontroller: fewer op-codes, more bit handling Instructions, and also it is defined as a device that includes micro processor, memory, & input / output signal lines on a single chip.
11. What is meant by LATCH? - Latch is a D- type flip-flop used as a temporary storage device controlled by a timing signal, which can store 0 or 1. The primary function of a Latch is data storage. It is used in output devices such as LED, to hold the data for display.
12. Why does microprocessor contain ROM chips? - Microprocessor contain ROM chip because it contain instructions to execute data.
13. What is the difference between primary & secondary storage device? - In primary storage device the storage capacity is limited. It has a volatile memory. In secondary storage device the storage capacity is larger. It is a nonvolatile memory. Primary devices are: RAM / ROM. Secondary devices are: Floppy disc / Hard disk.
14. Difference between static and dynamic RAM? - Static RAM: No refreshing, 6 to 8 MOS transistors are required to form one memory cell, Information stored as voltage level in a flip flop. Dynamic RAM: Refreshed periodically, 3 to 4 transistors are required to form one memory cell, Information is stored as a charge in the gate to substrate capacitance.
15. What is interrupt? - Interrupt is a signal send by external device to the processor so as to request the processor to perform a particular work.
16. What is cache memory? - Cache memory is a small high-speed memory. It is used for temporary storage of data & information between the main memory and the CPU (center processing unit). The cache memory is only in RAM.
17. What is called .Scratch pad of computer.? - Cache Memory is scratch pad of computer.
18. Which transistor is used in each cell of EPROM? - Floating .gate Avalanche Injection MOS (FAMOS) transistor is used in each cell of EPROM.
19. Differentiate between RAM and ROM? - RAM: Read / Write memory, High Speed, Volatile Memory. ROM: Read only memory, Low Speed, Non Voliate Memory.
20. What is a compiler? - Compiler is used to translate the high-level language program into machine code at a time. It doesn.t require special instruction to store in a memory, it stores automatically. The Execution time is less compared to Interpreter.
21. Which processor structure is pipelined? - All x86 processors have pipelined structure.
22. What is flag? - Flag is a flip-flop used to store the information about the status of a processor and the status of the instruction executed most recently
23. What is stack? - Stack is a portion of RAM used for saving the content of Program Counter and general purpose registers.
24. Can ROM be used as stack? - ROM cannot be used as stack because it is not possible to write to ROM.
25. What is NV-RAM? - Nonvolatile Read Write Memory, also called Flash memory. It is also know as shadow RAM.

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Intel interview questions

The following questions are used for screening the candidates during the first interview. The questions apply mostly to fresh college grads pursuing an engineering career at Intel.

1. Have you studied buses? What types?
2. Have you studied pipelining? List the 5 stages of a 5 stage pipeline. Assuming 1 clock per stage, what is the latency of an instruction in a 5 stage machine? What is the throughput of this machine ?
3. How many bit combinations are there in a byte?
4. For a single computer processor computer system, what is the purpose of a processor cache and describe its operation?
5. Explain the operation considering a two processor computer system with a cache for each processor.
6. What are the main issues associated with multiprocessor caches and how might you solve them?
7. Explain the difference between write through and write back cache.
8. Are you familiar with the term MESI?
9. Are you familiar with the term snooping?
10. Describe a finite state machine that will detect three consecutive coin tosses (of one coin) that results in heads.
11. In what cases do you need to double clock a signal before presenting it to a synchronous state machine?
12. You have a driver that drives a long signal & connects to an input device. At the input device there is either overshoot, undershoot or signal threshold violations, what can be done to correct this problem?
13. What are the total number of lines written by you in C/C++? What is the most complicated/valuable program written in C/C++?
14. What compiler was used?
15. What is the difference between = and == in C?
16. Are you familiar with VHDL and/or Verilog?
17. What types of CMOS memories have you designed? What were their size? Speed?
18. What work have you done on full chip Clock and Power distribution? What process technology and budgets were used?
19. What types of I/O have you designed? What were their size? Speed? Configuration? Voltage requirements?
20. Process technology? What package was used and how did you model the package/system? What parasitic effects were considered?
21. What types of high speed CMOS circuits have you designed?
22. What transistor level design tools are you proficient with? What types of designs were they used on?
23. What products have you designed which have entered high volume production?
24. What was your role in the silicon evaluation/product ramp? What tools did you use?
25. If not into production, how far did you follow the design and why did not you see it into production?

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Embedded systems interview questions

1. Can structures be passed to the functions by value?
2. Why cannot arrays be passed by values to functions?
3. Advantages and disadvantages of using macro and inline functions?
4. What happens when recursion functions are declared inline?
5. Scope of static variables?
6. Difference between object oriented and object based languages?
7. Multiple inheritance - objects contain howmany multiply inherited ancestor?
8. What are the 4 different types of inheritance relationship?
9. How would you find out the no of instance of a class?
10. Is java a pure object oriented language? Why?
11. Order of constructor and destructor call in case of multiple inheritance?
12. Can u have inline virtual functions in a class?
13. When you inherit a class using private keyword which members of base class are visible to the derived class?
14. What is the output of printf("\nab\bcd\ref"); -> ef
15. #define cat(x,y) x##y concatenates x to y. But cat(cat(1,2),3) does not expand but gives preprocessor warning. Why?
16. Can you have constant volatile variable? Yes, you can have a volatile pointer?
17. ++*ip increments what? it increments what ip points to
18. Operations involving unsigned and signed — unsigned will be converted to signed
19. a+++b -> (a++)+b
20. malloc(sizeof(0)) will return — valid pointer
21. main() {fork();fork();fork();printf("hello world"); } — will print 8 times.
22. Array of pts to functions — void (*fptr[10])()
23. Which way of writing infinite loops is more efficient than others? there are 3ways.
24. # error — what it does?
25. How is function itoa() written?
26. Who to know wether systemuses big endian or little endian format and how to convert among them?
27. What is interrupt latency?
28. What is forward reference w.r.t. pointers in c?
29. How is generic list manipulation function written which accepts elements of any kind?
30. What is the difference between hard real-time and soft real-time OS?
31. What is interrupt latency? How can you recuce it?
32. What is the differnce between embedded systems and the system in which rtos is running?
33. How can you define a structure with bit field members?
34. What are the features different in pSOS and vxWorks?
35. How do you write a function which takes 2 arguments - a byte and a field in the byte and returns the value of the field in that byte?
36. What are the different storage classes in C?
37. What are the different qualifiers in C?
38. What are the different BSD and SVR4 communication mechanisms

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Computer architecture and design interview questions

1. What is pipelining?
2. What are the five stages in a DLX pipeline?
3. For a pipeline with ‘n’ stages, what’s the ideal throughput? What prevents us from achieving this ideal throughput?
4. What are the different hazards? How do you avoid them?
5. Instead of just 5-8 pipe stages why not have, say, a pipeline with 50 pipe stages?
6. What are Branch Prediction and Branch Target Buffers?
7. How do you handle precise exceptions or interrupts?
8. What is a cache?
9. What’s the difference between Write-Through and Write-Back Caches? Explain advantages and disadvantages of each.
10. Cache Size is 64KB, Block size is 32B and the cache is Two-Way Set Associative. For a 32-bit physical address, give the division between Block Offset, Index and Tag.
11. What is Virtual Memory?
12. What is Cache Coherency?
13. What is MESI?
14. What is a Snooping cache?
15. What are the components in a Microprocessor?
16. What is ACBF(Hex) divided by 16?
17. Convert 65(Hex) to Binary
18. Convert a number to its two’s compliment and back
19. The CPU is busy but you want to stop and do some other task. How do you do it?

Hardware design interview questions

1. Give two ways of converting a two input NAND gate to an inverter
2. Given a circuit, draw its exact timing response. (I was given a Pseudo Random Signal Generator; you can expect any sequential ckt)
3. What are set up time & hold time constraints? What do they signify? Which one is critical for estimating maximum clock frequency of a circuit?
4. Give a circuit to divide frequency of clock cycle by two
5. Design a divide-by-3 sequential circuit with 50% duty circle. (Hint: Double the Clock)
6. Suppose you have a combinational circuit between two registers driven by a clock. What will you do if the delay of the combinational circuit is greater than your clock signal? (You can’t resize the combinational circuit transistors)
7. The answer to the above question is breaking the combinational circuit and pipelining it. What will be affected if you do this?
8. What are the different Adder circuits you studied?
9. Give the truth table for a Half Adder. Give a gate level implementation of the same.
10. Draw a Transmission Gate-based D-Latch.
11. Design a Transmission Gate based XOR. Now, how do you convert it to XNOR? (Without inverting the output)
12. How do you detect if two 8-bit signals are same?
13. How do you detect a sequence of "1101" arriving serially from a signal line?
14. Design any FSM in VHDL or Verilog.
15. Explain RC circuit.s charging and discharging.
16. Explain the working of a binary counter.
17. Describe how you would reverse a singly linked list.